Conventionally, in active-matrix flat-panel displays (FPD) such as liquid crystal displays or organic EL displays, thin-film semiconductor devices for display (hereafter simply referred to as a “thin-film semiconductor device”) also referred to as thin-film transistors (TFT) have been used for driving pixels.
Among the displays, the organic EL displays are current-driven devices unlike voltage-driven liquid crystal displays. Accordingly, there is an urgent need for developing a thin-film semiconductor device having excellent on-off characteristics as a driving circuit in an active matrix display device.
Conventionally, as a thin-film semiconductor device for the driving circuit in the liquid crystal display, a thin-film semiconductor device using a single-layer non-crystalline semiconductor layer (amorphous semiconductor layer) such as amorphous silicon as a channel layer has been used. This type of thin-film semiconductor device has a large band gap, and thus the off-state current is low. However, there is a problem that the on-state current is low as well due to low mobility.
There is another thin-film semiconductor device for the driving circuit in the liquid crystal display, in which a single-layer polycrystalline semiconductor layer has been used as the channel layer. This type of thin-film semiconductor device has high mobility of carriers and thus has a large on-state current, contrary to the thin-film semiconductor device using the single-layer non-crystalline semiconductor layer as the channel layer. However, there is a problem that the off-state current is also high due to the high carrier mobility.
In view of these problems, in the driving circuit of the organic EL display, a thin-film semiconductor device in which a two-layered structure including a first channel layer made of polycrystalline semiconductor layer and a second channel layer made of a non-crystalline semiconductor layer has been developed.
The patent literature 1 discloses a method for forming the polycrystalline semiconductor layer. The method for forming the polycrystalline semiconductor layer disclosed in the patent literature 1 features crystallizing an amorphous silicon film by annealing a substrate on which the amorphous silicon film is formed at a temperature in a range from 800° C. to 1000° C.